"Image may differ from actual product"
Roll over image to zoom in Click on image to zoom
This item is a Special Order and may take additional shipping time.
Place your order with SAITECH, and we will make every effort to have the item delivered to you as soon as possible.
How We Process Orders
Fastest Shipping: To get your products to you as quickly as possible, most orders placed directly by one of our several leading distributors or by the product's manufacturer. As a result, no one can get your orders to you faster than we can!
Strong Industry Alliances: SAITECH maintains long-standing alliances with the industry's leading distributors and manufacturers. As a result, we are the top source for your computer, office and Server technology needs.
Lowest Possible Prices: Advanced electronic interfaces continually scan our distributors for their best current pricing and availability. While changes in availability between different distributors may result in some price fluctuations, it ensures that you will always receive the lowest possible prices on currently available products!
Realtime Inventory: Live inventory updates are not available for this product.
Description
Specifications
Mfr Part Number: AB28L72Q8SHC4S
Condition: OEM
Brand: ATP Electronics
Model Number: AB28L72Q8SHC4S
Type: Memory Module
Short Description
ATP 1GB PC3200 DDR-4000MHz ECC Registered CL3 184Pin DIMM Memory Module RoHS Compliant (AB28L72Q8SHC4S)
Technical Description
Manufacturer: ATP
Manufacturer Part #: AB28L72Q8SHC4S
Memory Type: DDR SDRAM
Capacity: 1GB
Pins: 184 Pin
Bus Type: PC-3200
Error Correction: Registered ECC
Cycle Time: 5ns
Cas: CL3
Data Transfer Rate: 400Mhz
Memory Clock: 200Mhz
Rank: Rank 2
Voltage: 2.5
Features
200MHz Clock, 400Mbps data rate.
VDD= +2.6V ± 0.10V, VDDQ= +2.6V ± 0.10V
Double-data-rate architecture; two data transfers per clock cycle Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16) Bidirectional data strobe(DQS) Four banks operation Differential clock inputs(CK and /CK) DLL aligns DQ and DQS transition with CK transition MRS cycle with address key programs
Read latency 3 (clock) for DDR 400
All inputs except data & DM are sampled at the positive going edge of the system clock(CK) Data I/O transactions on both edges of data strobe Edge aligned data output, center aligned data input LDM, UDM for write masking only (x16) DM for write masking only (x4, x8) Auto & Self refresh 7.8µs refresh interval(8K/64ms refresh) Maximum burst refresh cycle : 8 54pin sTSOP II-400 & 66pin TSOP II & 60Ball FBGA Pb or Pb-Free package(RoHS compliant)
*Product descriptions, images, and part numbers are subject to change and may not accurately reflect manufacturer product alterations. For the latest and most precise information, kindly refer to the manufacturer's website and use the item's manufacturer part number.
You may also like
Recently viewed
- Opens in a new window.